A phase-locked loop (PLL) is a system that uses feedback to maintain an output signal in a specific relationship with a reference signal. Typically, a phase-locked loop contains a phase detector, a loop filter and a voltage-controlled oscillator (VCO). Phase-locked loops are used in many areas of electronics to control the frequency and/or phase of a signal. Applications include frequency synthesizers, modulators, demodulators and clock recovery circuits.
A typical phase-locked loop has three operational modes: 1) a free running mode, wherein no reference input signal is applied to the phase detector; 2) a capture or acquisition mode, wherein an output signal from the voltage controlled oscillator is different from the reference input signal and the voltage controlled oscillator is in the process of continually changing a phase of its output signal until the output signal maintains the same phase as the referenced input signal;and 3) a locked mode, wherein the voltage controlled oscillator output signal tracks and varies exactly with the phase of the reference input signal.
In the capture or acquisition mode, a loop filter having a wide bandwidth is preferred because it has a faster acquisition time for acquiring the reference input signal. Once the reference input signal is acquired, a narrower bandwidth is preferred for the locked mode of operation. Therefore, during the acquisition mode the loop bandwidth should be made as wide as possible to maintain good tracking and acquisition properties, and in the locked mode the loop bandwidth should be made as narrow as possible to minimize phase jitter in an output signal from the voltage controlled oscillator.
The need for a loop filter having both a wide bandwidth and a narrow bandwidth presents a problem because design criteria for the loop filter changes depending on the mode of operation, e.g., acquisition mode or locked mode.
The need for varying the requirements of a loop filter bandwidth is illustrated when a phase-locked loop is utilized to function as a band pass filter. Computer aided ranging systems often utilize phase-locked loops in such a manner. It is desirable that the phase-locked loop acquire a signal as quickly as possible to conserve computer time. Accordingly, during the acquisition mode of operation, the time constant of the phase-locked loop filter must be as short as possible and the bandwidth, therefore, as wide, as possible. However, for the phase-locked loop to properly perform the friction of a bandpass filter, a predetermined loop bandwidth must be maintained during the locked state. A bandwidth in the locked mode of operation is typically less than the bandwidth in the acquisition mode of operation.
One approach to solving the problem of loop filter bandwidth has been to utilize a "passive loop filter" that includes first and second resistors and a capacitor serially connected between the input terminal of the loop filter and ground. Two oppositely poled diodes are connected in parallel across the first resistor. The output signal of the phase comparator is applied to the first resistor and the output signal of the loop filter is taken across the second resistor and capacitor. During the acquisition mode a differential voltage exists across the diodes and current flows through the diodes. The first resistor is thus bypassed and, in effect, removed from the filter. When phase-lock is reached, an equipotential exists across the diodes, and the diodes accordingly become non-conductive. The first resistor is thereby made a factor in determining the time constant of the loop filter. During the locked mode, the phase-locked loop maintains a predetermined narrow bandwidth and, during the acquisition mode when the first resistor is not a factor in determining the loop filter time constant, the loop bandwidth is broadened to achieve faster acquisition.
However, the "passive loop filter" is not suitable for use in various types of PLL's. For example, it is desirable to have a PLL which locks on frequency as well as phase, and one that will not falsely "lock" onto reference input signals that are close to harmonics of the VCO center frequency.
Similar methods have been offered to provide different time constants corresponding to the modes of operation, but such methods have their own shortcomings. . For example, U.S. Pat. No. 3,993,958 issued to Cutsogeorge, discusses a loop filter circuit for speeding acquisition in a phase-locked loop by utilizing two resistor-capacitor filter circuits interconnected by a pair of diodes. Each filter circuit has a different time constant. However, the approach taken in the '958 patent only works with analog phase detectors. If the teachings were applied to a digital, comparator-type phase detector, the output pulses from the phase detector would be coupled directly into the VCO input by the diodes yielding undesirable instability in the circuit.
What is needed is a more versatile phase-locked loop system that allows for the fast acquisition of analog and digital reference input signals and a phase-locked loop system that provides a more narrow bandwidth signal to the VCO once the signal has been acquired. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a phase-locked loop system having an improved loop filter design for optimizing performance in an acquisition mode and a locked mode of operation.